The present invention relates to a semiconductor integrated circuit device and, more particularly, to a gate array of an ECL (emitter coupled logic) type, which is manufactured in a master-slice method.
Conventionally, an ECL type gate array employs a master substrate in which a number of basic cells each having a plurality of resistors and a plurality of transistors are disposed in a matrix form. In such an ECL type gate array, by means of wiring process, each of the necessary logic blocks is formed with use of one or several basic cells and such logic blocks are interconnected therebetween for achieving the desired functions.
A conventional logic circuit constituted by a basic cell is shown in FIG. 4. In forming the logic circuit in conventional ways, the transistor to be used for a constant current source and the transistors for constituting a differential circuit within the basic cell have been predetermined and also the resistors to be connected to the respective transistors have been predetermined. Therefore, the conventional logic circuit thus formed for a given function can be used only as a circuit performing that particular function. The full description of and problems in such a conventional logic circuit are given later.